Circuit Model
The quantum circuit model represents a computation as an ordered network of quantum systems and operations. Quantum wires carry subsystem state from one operation to the next. Gates act on one or more wires. Measurements produce classical records, and those records may control later operations. A complete circuit specification also states how inputs are prepared, what counts as output, and which resources are being counted.
In the ideal unitary form, an -qubit input is transformed by a sequence of local unitary gates and measured at the end. The more general and operationally complete form allows mixed states, channels, mid-circuit measurements, discarding, reset, and classical feedforward. It is then a composition of quantum channels or instruments rather than one unitary matrix.
To calculate what a diagram does, fix the wire order, operation sequence, input state and output being read. Counting its cost additionally requires a gate set, connectivity and scheduling rules.
Helpful background. Qubits and encodings explains registers; density operators treats mixed states and conditional outputs; tensor-product ordering translates between matrix and wire conventions.
Registers and Basis Conventions
Section titled “Registers and Basis Conventions”An -qubit register has Hilbert space
Choose and state the tensor-factor order. This page uses
where . The computational basis has vectors, but this exponential dimension does not imply that a circuit can read out independent classical values.
Software libraries disagree about bitstring display order, integer endianness, and which matrix factor corresponds to the top wire. Those are coordinate conventions, not physical differences. A trustworthy calculation declares:
- the top-to-bottom wire order;
- the tensor-product order;
- how a displayed bitstring maps to an integer;
- whether outcome strings are printed in diagram order or reversed.
For example, in the tensor order above, has its first qubit excited, regardless of whether software prints the associated classical bits as 100 or 001. Follow the explicit mapping rather than inferring it from an integer label.
Registers need not be qubits. A qudit wire may carry , a bosonic wire may carry a mode, and an encoded logical wire may denote a code subspace spread over many physical systems. The circuit grammar survives, but the allowed gates, measurements, leakage modes, and resource units change.
The chapter guide links the mode, bosonic-encoding and topological computation models. Each specifies how its physical systems represent logical registers.
What a Wire Means
Section titled “What a Wire Means”A quantum wire denotes the identity connection between two operation ports. It says that the output subsystem of one operation is the input subsystem of the next. It does not assert that the wire carries a hidden classical bit, and it need not trace the literal trajectory of one microscopic particle.
Standard diagrams place time from left to right and registers from top to bottom. If a page or software tool uses another convention, it must say so.
The following distinctions matter:
- A line crossing can be mere graphical overlap or can specify a wire permutation, depending on the notation. Track the named endpoints and the stated meaning of the crossing.
- Relabeling two tensor factors changes notation; applying a SWAP gate changes the quantum state relative to fixed labels.
- A wire cannot branch to copy an unknown state. A controlled-NOT gate has two input and two output wires; it is not a fanout node.
- A discarded wire represents a partial trace or channel output that is no longer retained.
- A newly initialized wire represents a preparation map, commonly , not a unitary acting on nothing.
Gates and Their Embedding
Section titled “Gates and Their Embedding”An ideal gate acting on a register subset is a unitary . A one-qubit gate acting on embeds as
For gates on several nonadjacent wires, the tensor-factor order must be handled explicitly. One may use permutation operators, index notation, or a structured circuit library, but silently reshaping a matrix is not a convention.
A -qubit gate is local in the circuit sense when is bounded independently of the total input size. Treating an arbitrary -qubit unitary as one elementary gate hides an exponentially large matrix and destroys meaningful gate-count claims.
Operators on composite systems develops these embeddings; single-qubit gates and multi-qubit gates give concrete matrices. Universal gate sets explains how they generate more general operations.
Time Order and Matrix Order
Section titled “Time Order and Matrix Order”Suppose the diagram applies gates from left to right. State evolution is
so the complete unitary is
The earliest gate is nearest the state vector and therefore appears on the right in the matrix product. “Read the picture left to right; apply the algebra right to left” is a useful check.
Gates on disjoint wire sets commute after embedding:
They can therefore occupy the same ideal parallel layer. Gates that share a wire cannot be in the same layer, even if their matrices happen to commute, unless the execution model explicitly supports a simultaneous composite operation.
(a) Quantum wires carry an ordered register through , controlled-NOT, and computational-basis measurements. (b) A measured classical record controls a later operation; this is different from coherent quantum control. (c) Width, gate count, and depth depend on the chosen gate and parallelism model.
Pure, Mixed, and Dynamic Circuits
Section titled “Pure, Mixed, and Dynamic Circuits”Ideal unitary circuit
Section titled “Ideal unitary circuit”For a closed circuit with input state , the final state before measurement is
If an output register is measured in the computational basis and all other retained systems are denoted , then
The circuit outputs a sample from unless the specification asks for a retained quantum state or an estimated expectation value. One run does not reveal every amplitude.
Channels, discard, and reset
Section titled “Channels, discard, and reset”A physical or generalized circuit may contain completely positive trace-preserving maps:
Unitary gates are the special channels
Preparation, noise, reset, and discarding are naturally channels. Composing fixed maps on the displayed register assumes that each map describes that stage with the information retained so far. If an environment carries memory between stages, include that memory in the state or use a multi-time process description; independently fitted reduced channels need not compose correctly. A circuit that includes them need not have one unitary description on the displayed wires, although a larger unitary dilation may exist after adding environments and ancillas.
Measurements and records
Section titled “Measurements and records”A measurement instrument has completely positive, trace-nonincreasing outcome maps whose sum is trace preserving. For input ,
and, when ,
If the record is retained, the output is a classical–quantum state:
The branch maps are generally trace nonincreasing. Their traces are probabilities, so normalizing every branch before recording those probabilities loses part of the circuit semantics.
Quantum Control and Classical Control
Section titled “Quantum Control and Classical Control”A coherently controlled unitary is itself a unitary gate:
The control wire may be in a superposition and can become entangled with the target. No classical outcome exists merely because the diagram contains a control dot.
Classical control is different. A measurement first produces a record , and a later channel is selected from that record. If the record is retained,
If it is forgotten, sum over . The resulting map can be irreversible even when every conditional is unitary.
Under suitable conditions, a measurement used only to control later gates can be deferred by replacing classical control with coherent control and measuring later. This deferred-measurement principle is a model equivalence, not a claim that real-time measurement has no cost. Deferral may require extra coherent ancillas, change connectivity and depth, remove useful resets, or alter the physical noise exposure.
Measurement in circuits develops the basis rotations and readout rules. Mid-circuit measurement and feedforward treats causal branching, reset, reuse and the conditions for deferred measurement.
Input Conventions
Section titled “Input Conventions”The same diagram can answer different questions depending on its input: Common forms include:
- Fixed input: all data and ancillas begin in .
- Classical input: a bitstring is encoded as or used to select gates.
- Quantum input: an arbitrary state enters a named register, possibly entangled with an inaccessible reference .
- Oracle access: a callable operation supplies information about a function or physical model. Its allowed inputs and permitted forward, inverse or controlled uses must be specified; see quantum oracles.
- Sample input: classical data are drawn from a stated distribution and encoded by a preparation procedure whose cost may matter.
- Advice or resource state: a state is supplied externally. Its preparation cost matters unless the model explicitly supplies it for free. For example, measurement-based computation consumes an entangled resource state. In complexity theory, advice can be nonuniform: it depends on input length without an efficient preparation rule.
Ancillas should be named and initialized. Assuming an unlimited supply of clean ancillas can change width, depth, reversibility, and fault-tolerance costs.
Output and Success Conventions
Section titled “Output and Success Conventions”The output may be:
- a classical bit or bitstring;
- a sample from a target distribution;
- an estimate of an expectation value after many shots;
- a retained quantum state or channel;
- a success flag plus a conditional state;
- an accepted or rejected decision with bounded error.
For a classical input and output , write the induced conditional distribution as
For a postselected circuit, report both
A high conditional fidelity with exponentially small success probability is not a high-rate algorithm.
Circuit equivalence also depends on the output contract. Two closed circuits may implement the same unitary up to global phase. Two open circuits may implement the same channel. Two sampling circuits may have the same measured distribution while producing different unmeasured states. State which equivalence is relevant.
Width, Size, Depth, and Other Resources
Section titled “Width, Size, Depth, and Other Resources”Resource counts are meaningful only relative to a gate library and execution model.
| Resource | Operational definition | Important dependence |
|---|---|---|
| Width | Maximum number of simultaneously live quantum wires | Includes data, ancillas, routing, syndrome, and workspace qubits |
| Gate count or size | Number of elementary gates | Depends on the declared gate set and approximation tolerance |
| Depth | Minimum number of allowed parallel layers respecting dependencies | Depends on connectivity, parallelism, and scheduling assumptions |
| Two-qubit gate count | Number of elementary gates acting on two qubits | Includes nonentangling gates such as SWAP if they are elementary; an entangling-gate count is a different convention |
| Query count | Calls to a specified oracle | Does not include ordinary gates unless stated |
| Measurement rounds | Sequential layers of measurement and feedforward | Depends on classical latency and adaptivity |
| count and depth | Non-Clifford resources in a fault-tolerant decomposition | Depends on code, synthesis target, and available resource states |
| Shot count | Repeated circuit executions used for statistical estimation | Depends on variance, confidence, mitigation, and grouping |
If the elementary gates can be partitioned into layers whose gates have disjoint supports, then
with
This schedule has depth ; the minimum depth requires minimizing over all allowed schedules of the specified operations. Hardware routing can add SWAPs; calibration can prohibit simultaneous gates; measurement and feedforward can introduce latency; fault-tolerant protocols can replace one logical gate with a large spacetime structure. A circuit depth quoted without those assumptions is not a wall-clock runtime.
Circuit Families and Uniformity
Section titled “Circuit Families and Uniformity”One finite circuit can act on every input of its fixed register size. To handle arbitrarily growing input sizes, an algorithm is usually specified by a family
indexed by input size. The family is uniform when a classical procedure generates the description of efficiently from . Uniformity prevents exponentially complicated answers from being hidden in an unexplained circuit description.
Complexity claims also need:
- a fixed finite or efficiently describable gate set;
- bounded gate locality;
- an approximation metric and tolerance;
- efficient classical descriptions of gate parameters;
- a clear oracle or advice model.
Counting an arbitrary unitary as one gate is formally a circuit but not an informative computational model. Its matrix requires exponentially many parameters in general.
Adiabatic computation provides a Hamiltonian-based model with polynomial equivalence to circuits under suitable uniformity, locality, norm and precision assumptions.
Worked Example: Preparing and Measuring a Bell Pair
Section titled “Worked Example: Preparing and Measuring a Bell Pair”Use register order and input
Apply to :
Then apply controlled-NOT with as control and as target:
Thus the circuit unitary is
Computational-basis measurement gives
The joint state contains coherence between and , not just the classical correlation visible in this measurement. Measurements in other bases can test that distinction. Under the elementary gate set , the preparation has width , gate count , and depth . The two terminal measurements can occur in one measurement layer.
Circuit Model versus Hardware Execution
Section titled “Circuit Model versus Hardware Execution”An abstract circuit is neither a pulse schedule nor a device schematic.
- A logical circuit specifies ideal operations on abstract or encoded systems.
- A compiled circuit rewrites those operations into a target gate set and connectivity graph.
- A scheduled circuit assigns compatible operations to time intervals.
- A control program produces pulses, voltages, optical fields, and readout decisions.
- A physical execution realizes noisy channels whose parameters drift and must be estimated.
These layers should not be collapsed when reporting depth, fidelity, runtime, or resource advantage. One logical controlled-NOT may be native on one platform, compiled from several interactions on another, or implemented fault tolerantly by code deformation, lattice surgery, teleportation, or magic-state-assisted gadgets. Hardware overview compares physical implementations.
Correctness and Error Metrics
Section titled “Correctness and Error Metrics”The correct comparison depends on the output object.
- Compare pure output states up to global phase.
- Use trace distance or fidelity for states, with conventions stated.
- Use a channel metric such as diamond distance for worst-case process error.
- Use total variation distance for classical output distributions.
- Use an explicit failure probability for bounded-error decision or postselected circuits.
- Use an application-level observable error when that is the promised output.
Average gate fidelity alone does not determine a long circuit’s output error. Coherent errors can accumulate, correlations can invalidate independent-noise estimates, and postselection can hide failure probability. Noise in Quantum Information develops the practical taxonomy and diagnostic consequences. The Fidelity and Trace Distance entries provide compact state formulas; general channel theory remains in the open-systems volume.
Quantum channels for information processing explains how to model noisy operations. Error correction and fault tolerance addresses how a circuit can remain reliable when these operations are imperfect. For implementing the circuit, continue to gate decomposition, mapping and routing, or circuit simulation.
Exercises
Section titled “Exercises”- Embedding gates into an ordered register. Use the convention
Write the operator that applies to , and evaluate it on . Then evaluate a controlled-NOT from to on .
Solution
The embedded one-qubit gate is
It flips only the middle factor:
For , the first qubit is the control and the third is the target. Because the control value in is ,
Neither calculation can be inferred safely from an integer label unless the bit and tensor orders have first been declared.
- Diagram order versus operator order. A one-qubit circuit applies and then from left to right to input . Find the final state. What state results if the matrix product is reversed by mistake?
Solution
The first gate is , so the correct circuit unitary is
Therefore
The mistaken product is . Since ,
The two states have the same computational-basis probabilities but opposite -basis outcomes, so the ordering error is physically observable.
- Bell-circuit output. Starting from , apply to the first qubit and then . Compute the final density operator, both one-qubit reduced states, and the computational-basis output distribution.
Solution
The state-vector calculation gives
The density operator is
Tracing out either subsystem removes the coherence terms and gives
Terminal computational-basis measurement gives
Each local result is random, while the joint results are perfectly correlated.
- Gate count and parallel depth. A three-qubit circuit has five gates with these dependencies:
- and have no predecessors;
- follows ;
- follows ;
- follows both and .
Find the gate count, width, and minimum ideal depth when gates on disjoint supports may run in parallel.
Solution
There are five elementary gates and three live wires, so
A valid schedule is
The gates within each of the first two layers act on disjoint supports. The final controlled- must wait for both predecessor branches, so no two-layer schedule satisfies the dependencies. Hence
Connectivity or calibration constraints could increase the physical depth.
- Why a CNOT is not a cloning branch. Let
Apply a controlled-NOT to . Compare the result with .
Solution
Linearity gives
A true clone would be
These states are unequal for a generic superposition. The controlled-NOT copies the computational-basis label when the input is or ; on a superposition it generally creates entanglement. A branching wire would incorrectly assert universal cloning.
- Measurement-based active reset. Measure one qubit in the computational basis, obtaining , and then apply . Show that the unconditioned output is for every input density operator . What information remains in the classical record?
Solution
Let
The unnormalized measurement branches are . After the conditional corrections,
Forgetting the record gives
The retained classical record has probabilities
It remembers the measured computational-basis population even though the corrected quantum output is always reset. The input coherence is destroyed, so this displayed-wire operation is not unitary. If the input qubit was correlated with an inaccessible reference , the unconditioned result is . For a Bell input, the recorded bit remains classically correlated with , even though the reset qubit is now uncorrelated with both. Resetting a local wire does not reconstruct its previous joint quantum state.
References
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