Fault-Tolerant Quantum Computing

Fault-tolerant computing research asks how independently demonstrated protection mechanisms can be integrated into a sustained, useful logical computation. This page preserves a historical snapshot with evidence cutoff 11 August 2026. It is not a refreshed assessment of October 2026 and should not be used as a current platform ranking or an exhaustive milestone census.

The argument, source attributions, and project design were technically reviewed on 11 October 2026. That review date does not extend the historical milestone cutoff.

Status at the cutoff. Repeated correction, bounded logical-memory scaling, protected gates, and logical resource-state transformations were established in specified experiments. Integration at the scale, duration, throughput, and validation required by a useful general-purpose workload remained an active, engineering-limited question in this assessment. The selected results below do not by themselves establish that complete capability.

Helpful background. The fault-tolerant architecture bridge owns the stable evidence ladder, failure budgets, logical-operation contracts, and decoder/control requirements. Error-correction case studies explains how to audit physical reference channels, postselection, and scaling.

Fault-tolerant computing at the August 2026 cutoff

The evidence spans theorems, circuit simulations, individual hardware operations, and integrated subsystems. These categories answer different questions. A threshold theorem is conditional on a fault model and allowed operations; a successful finite experiment tests a particular physical implementation. Neither licenses extrapolation beyond its hypotheses or measured regime without further evidence.

The research question is how memory, logic, non-Clifford resources, routing, classical processing, calibration, and verification work together. The stable architecture criteria provide the common comparison language; the observations below supply dated examples rather than a single ranking.

Selected evidence at the cutoff

Surface-code memory and decoding. Google Quantum AI and Collaborators reported a distance-7 memory using 101 qubits with logical error per cycle $1.43(3)\times10^{-3}$ and error-suppression factor $2.14(2)$ for increasing distance by two. A distance-5 experiment integrated a real-time decoder with average latency $63\,\mu\mathrm{s}$ over runs up to one million cycles. These are memory and decoder results at specified operating points, not a measurement of a universal workload’s delivered error or runtime. Primary report.

The paper’s 2026 author correction changes Figure 3a’s labeling to identify repetition-code distance and the reference datasets correctly. Its rare-event study should therefore not be read as distance-29 surface-code evidence. Also distinguish latency from throughput: a decoder can process a continuous syndrome stream with a pipeline whose output lags by many cycles. The $63\,\mu\mathrm{s}$ average latency and $1.1\,\mu\mathrm{s}$ cycle time are not contradictory; whether that lag is tolerable depends on when a logical decision actually needs the decoded frame.

Color-code scaling and operations. Lacroix and colleagues compared repeated distance-3 and distance-5 color-code memories and studied protected logical operations on a superconducting processor. The distance comparison and the operation experiments must retain their own circuits, observables, and acceptance conditions; their existence does not establish an unrestricted large-scale gate set. Primary report.

Small-code universal gates. Postler and colleagues demonstrated a fault-tolerant universal set using two logical qubits on trapped-ion hardware, including a logical CNOT and a T gate implemented by magic-state injection. This supplies evidence about protected small-code operations and their reference comparison. Useful-scale repeated computation is an additional claim. Primary report.

Neutral-atom integration. Bluvstein and colleagues used reconfigurable arrays of up to 448 atoms to implement and study elements of a universal fault-tolerant architecture. The relevant evidence is the particular combination of correction, logical operations, movement, and reuse studied in the experiments. The architecture’s title must not be substituted for a verified end-to-end useful workload. Primary report.

Logical magic-state distillation. Sales Rodriguez and colleagues performed logical distillation using distance-3 and distance-5 color codes on a neutral-atom device and observed improved output logical-state fidelity. Factory throughput, acceptance, routing, and correlated errors still have to be matched to a compiled algorithm’s demand. Primary report.

Concatenated bosonic protection. Putterman and colleagues combined cat qubits with a distance-5 repetition code. The outer code corrected phase flips, while the bosonic mechanism suppressed bit flips. Reported phase-flip suppression and remaining bit-flip contributions must be assessed separately; the protected channel alone does not characterize the complete logical channel. Primary report.

Calibration coupled to QEC. Sivak and colleagues used syndrome events as a learning signal for control adaptation and reported improved logical stability under injected drift on superconducting hardware. Their report separates device experiments from numerical scaling studies. It is evidence for a control mechanism under tested conditions, not a demonstration of unlimited autonomous operation or unbiased adaptation through a useful algorithm. Primary report.

Low-overhead theoretical architectures. Finite-block qLDPC simulations, constant-space-overhead protocols, and logical-measurement constructions address different resource bottlenecks. Their dated evidence is recorded in Quantum LDPC Codes. A theorem or simulated crossover remains conditional on its circuit, connectivity, noise, and classical-processing assumptions.

These observations support multiple bounded milestones. The common unresolved step in this snapshot was sustained integration: matched logical protection, universal resources, latency, yield, and a verified useful workload in the same complete system.

Open problems retained from the cutoff

Integrate memory and computation

Memory experiments are the cleanest place to test repeated correction, but an algorithm repeatedly changes stabilizers, consumes ancillas, moves information, and performs adaptive measurements. The resulting circuit has more boundaries and fault mechanisms than an idle logical patch.

The decisive scaling experiment is not simply a longer memory. It is a family of logical circuits whose error per useful operation decreases as protection increases, while the gate set, acceptance rule, and classical pipeline remain operationally comparable.

Resolve rare correlated faults and error floors

Below-threshold fits are often measured where logical failures are frequent enough to estimate. Useful algorithms demand rates many orders of magnitude lower. At that scale, rare bursts, radiation events, common-mode control errors, leakage cascades, decoder-model mismatch, and long-memory noise can dominate.

A simple floor model illustrates the issue:

$$p_{\mathrm L}(d) = A\Lambda^{-(d+1)/2} +p_{\mathrm{floor}}.$$

Increasing $d$ suppresses the first term but not $p_{\mathrm{floor}}$. Establishing a target near $10^{-12}$ therefore cannot rest only on a fit made near $10^{-3}$. It needs physical fault studies, accelerated tests, independent monitors, code families sensitive to different correlations, and long observation windows. A floor is not necessarily fundamental; it identifies a fault source that the present architecture does not suppress.

Make universal resources a production system

The Eastin–Knill theorem prevents a nontrivial exact finite-dimensional code from providing a universal set solely through transversal logical unitaries under its assumptions. Architectures add magic states, code switching, gauge fixing, teleportation, pieceable constructions, or other mechanisms.

The question in this snapshot was not whether such mechanisms exist. It is whether they can supply a large algorithm with:

• sufficiently low output error;
• adequate accepted-state throughput;
• bounded qubit and routing footprint;
• robust feedforward and frame management;
• tolerance to factory faults and outages;
• a verification record that catches correlated bad batches.

Parallel factories can reduce starvation but consume footprint and power. Larger distillation protocols can reduce output error but increase latency and sensitivity to correlated inputs. The optimal factory is workload- and architecture-dependent.

Magic State Distillation owns the established protocol mathematics, exact 15-to-1 map, factory failure modes, and bounded preparation-versus-distillation evidence. The open systems-integration milestone remains tracked here.

Reduce overhead without moving it off the ledger

High-rate codes, long-range coupling, biased-noise qubits, erasure conversion, transversal gates, and constant-overhead constructions can reduce a major term. Each can also transfer cost to connectivity, control, measurement, classical processing, or fabrication.

The qLDPC snapshot records theoretical protocols using high-rate codes and logical measurement to improve space or time overhead under stated assumptions. The integration problem is to turn those guarantees into finite circuit-level architectures with specified noisy components and a credible implementation path.

Scale the classical co-processor

Decoding is only one classical workload. A full machine also performs pulse generation, readout discrimination, leakage classification, calibration, logical scheduling, factory management, fault logging, and verification. These tasks compete for bandwidth and may run at different temperature stages.

The classical system must itself fail rarely enough for the quantum failure budget. Silent corruption of a frame bit can become a logical error. A robust architecture needs redundancy, checksums or consistency tests, bounded recovery behavior, and a specification for what happens when a deadline is missed.

Sustain operation through drift, defects, and repair

A useful computation may run for hours, days, or longer. During that time, qubits can drift, links can fail, traps can empty, couplers can detune, and readout models can age. Code deformation and spare resources may route around defects, but adaptation must not create untracked logical transformations.

The relevant metric is not the best calibrated hour. It is the distribution of delivered logical performance over the planned mission time, including maintenance and recovery.

Demonstrate end-to-end utility

Fault tolerance is a means, not a workload. A useful demonstration must state the computational question, required precision, data-access cost, classical baseline, verification method, and wall-clock resource ledger. A small logical algorithm can be scientifically valuable as an integration test without establishing practical advantage. Calling those two claims by different names improves rather than diminishes the experiment.

What Would Change the Assessment?

The historical assessment would need revision when evidence crossed a durable boundary, not whenever a larger component count is announced. Strong update triggers include:

• reproducible logical-error suppression over several increasing code distances for both memory and a universal logical operation set;
• sustained real-time decoding and control at a syndrome rate and mission duration relevant to a declared useful workload;
• a complete magic-state or alternative universal-resource pipeline whose measured output error and throughput meet a compiled circuit’s demand;
• an experimentally grounded architecture comparison that includes data, ancillas, factories, routing, spares, calibration, classical processing, yield, and delivered runtime;
• direct constraints on rare correlated faults at or below the algorithmic failure target;
• a fault-tolerant computation of scientific interest with a transparent verifier and a competitive end-to-end classical comparison;
• repeated results across devices or groups using an interoperable logical benchmark contract.

A million physical qubits would not by itself meet any of these triggers. A smaller system could meet several.

Graduate entry project: integrate the August evidence

This project was added on 11 October 2026 as a way to work with the retained historical record; it does not refresh that record’s evidence cutoff. Choose one small universal logical circuit and construct a dependency graph for memory, protected Clifford gates, non-Clifford resources, measurement and decoder decisions. Populate each operation with an experimentally measured range from a cited source, keeping incompatible platform assumptions visibly separate.

A laptop discrete-event model is enough. Deliver a schedule, failure budget, sensitivity plot and a list of parameters that cannot yet be grounded in one integrated device. Compare a serial baseline with a pipelined schedule. Failure tests halve resource-state throughput, double feedback latency and introduce a correlated-error floor. If the estimate depends on combining incompatible best-case measurements, the deliverable is that identified gap, not a forecast of a working machine.

The research extension is an experimentally testable interface improvement: for example, a decoder scheduling rule or resource-state buffering policy whose benefit survives realistic timing variation. The competing hypothesis is that another subsystem becomes limiting and removes the apparent gain.

Specify a workload and a falsifiable scheduling claim

Use a fixed small circuit with adaptive non-Clifford steps, and record which operations can proceed with a deferred Pauli frame and which must wait for a decision. Simulate arrivals, decoding completions, accepted factory outputs, buffer contents, and gate requests as separate events. The model is a study of scheduling assumptions; it does not establish that the cited subsystems can be combined on one device.

For a toy factory bank with $m$ identical factories, each attempting one output every $T_f$ seconds with independent acceptance probability $a$, the mean accepted supply is $ma/T_f$. A requested rate below that mean is only a necessary long-time capacity check. Finite buffers, bursty consumption, correlated rejection, and outages can still cause stalls. Compare a deterministic mean-rate model with a sampled event stream using the same mean; the change in delivered runtime measures the cost of variability.

Keep this separate from reliability. If $N$ relevant decision deadlines each have miss probability at most $p_{\rm miss}$, the union bound gives $P(\text{one or more misses})\leq Np_{\rm miss}$ without requiring independence. For $N=10^6$ and a $0.01$ deadline-failure budget, a sufficient bound is $p_{\rm miss}\leq10^{-8}$. A 99.9-percentile runtime says far less about such a mission. A missed deadline need not be a logical error if the architecture can safely pause; then count the added memory exposure and runtime instead. Define that recovery policy before comparing schedulers.

Know what the sample size can certify

For zero failures in $M$ independent Bernoulli trials of the same specified event, the exact one-sided 95% upper confidence limit is

$$p_U=1-0.05^{1/M}\simeq\frac{2.996}{M}.$$

Thus one million failure-free trials bound that event only near $3\times10^{-6}$, not $10^{-12}$. Correlated cycles cannot be counted as independent trials, and a memory-cycle bound cannot be substituted for a universal-gate bound. Rare-event models and accelerated sampling can be valuable, but their likelihood reweighting and physical assumptions need independent validation.

In weeks 1–2 reproduce an exactly schedulable serial circuit and a zero-noise limit. In weeks 3–4 reproduce one source’s timing distribution or use a clearly synthetic distribution with a matching summary. In weeks 5–6 compare buffering policies on withheld load patterns, reporting stall tails, accepted throughput, and the full failure budget. Continue only if an interface improvement survives realistic uncertainty; otherwise the useful result is the subsystem specification needed to make it viable.

Entry reading for the historical integration question

Begin with the surface-code paper and its correction for the distinction between scaling, rare faults, and real-time processing. Then compare the Postler protected-gate experiment with the Sales Rodriguez distillation experiment: they expose different interface requirements. Use the Bluvstein architecture study to see how several ingredients are combined, retaining its actual code choices and acceptance conditions. The Putterman and Sivak studies motivate alternative protection and control hypotheses. A new milestone matters here when its measured interface changes the workload budget, not only when its headline qubit count increases.

References

• D. Bluvstein et al., “A fault-tolerant neutral-atom architecture for universal quantum computation,” Nature 649, 39–46 (2026). doi:10.1038/s41586-025-09848-5
• B. Eastin and E. Knill, “Restrictions on transversal encoded quantum gate sets,” Physical Review Letters 102, 110502 (2009). doi:10.1103/PhysRevLett.102.110502
• Google Quantum AI and Collaborators, “Quantum error correction below the surface code threshold,” Nature 638, 920–926 (2025), with Author Correction, Nature 653, E5 (2026). article; correction
• N. Lacroix et al., “Scaling and logic in the colour code on a superconducting quantum processor,” Nature 645, 614–619 (2025). doi:10.1038/s41586-025-09061-4
• L. Postler et al., “Demonstration of fault-tolerant universal quantum gate operations,” Nature 605, 675–680 (2022). doi:10.1038/s41586-022-04721-1
• H. Putterman et al., “Hardware-efficient quantum error correction via concatenated bosonic qubits,” Nature 638, 927–934 (2025). doi:10.1038/s41586-025-08642-7
• Pedro Sales Rodriguez et al., “Experimental demonstration of logical magic state distillation,” Nature 645, 620–625 (2025). doi:10.1038/s41586-025-09367-3
• V. Sivak et al., “Reinforcement learning control of quantum error correction,” Nature 655, 879–884 (2026). doi:10.1038/s41586-026-10759-2