Quantum LDPC Codes: Evidence and Open Problems

Quantum LDPC research asks which sparse, high-rate code families can reduce the total cost of reliable logical computation once syndrome extraction, connectivity, decoding, logical operations, and hardware yield are counted. This page preserves a historical evidence snapshot with cutoff 11 August 2026. It has not been refreshed to the October 2026 research state and is not an exhaustive ranking of codes, decoders, or platforms.

The sources, numerical interpretation, and project design were technically reviewed on 11 October 2026; the selected historical milestone cutoff remains 11 August.

Status at the cutoff. Asymptotically good qLDPC families were established theoretically. Favorable finite-block circuit simulations, small hardware demonstrations, and low-overhead logical-operation protocols supplied distinct forms of evidence. A complete, useful-scale low-overhead hardware computer was not established by the selected record below; that integration question remained active and engineering limited.

Helpful background. Quantum LDPC codes owns the code definitions and constructions. The high-rate architecture bridge owns finite-block resource accounting, decoder throughput and latency, connectivity requirements, and logical addressability. The broader fault-tolerant computing snapshot places qLDPC proposals among other integration approaches.

Quantum LDPC evidence at the August 2026 cutoff

The evidence must distinguish four questions: whether an asymptotic family exists, whether a finite code and circuit perform well in a declared noise model, whether the hardware can implement that circuit, and whether the complete system delivers a useful logical workload at lower cost. Progress on one question does not silently settle the others.

The existence theorems are part of the stable code foundations. This record concentrates on the dated finite-code, decoder, and architecture evidence that motivated the remaining questions.

A finite-memory reference case

Bravyi and colleagues (2024) analyzed bivariate-bicycle memories with weight-6 checks and degree-6 connectivity decomposable into two planar subgraphs. The main text describes seven CNOT layers, whereas the abstract uses a depth-eight full-circuit convention. Report the operation layers being counted rather than conflating these two depth statements.

Their $[[144,12,12]]$ example uses 144 data and 144 check qubits. Under the specified circuit-level noise and decoding model, the study reported a threshold scale near $0.7\%$ and projected preservation of 12 logical qubits for nearly one million cycles at physical error $0.1\%$, compared with roughly 3000 physical qubits for its surface-code reference. These are simulation and model-based projection results, not a 288-qubit hardware memory record. Primary report.

A different range-dependent gate error, idle model, leakage process, decoder, logical operation requirement, or elapsed-time target can move that crossover. The comparison is valuable because it exposes a concrete architecture that can be tested, not because its ratio is universal.

Decoder evidence

Localized statistics. Hillmann and colleagues (2025) developed a reliability-guided decoding method designed for parallel treatment of local problems. Its circuit simulations test a specified algorithm and code/noise setting; robustness against cluster growth, missing checks, correlated faults, and deployment on a target classical processor remains a separate question. Primary report.

Beam search. Ye, Wecker, and Delfosse studied a BP-guided search whose width trades accuracy against runtime. For a studied bivariate-bicycle configuration at $p=5\times10^{-4}$, their width-32 implementation reported a 99.9-percentile runtime per extraction round below $1\,\mathrm{ms}$ on one CPU core. This is numerical and software-runtime evidence for the specified configuration; it does not imply the same deadline for a faster syndrome cycle or every code family. Primary report.

The stable decoder requirements include logical accuracy, sustained throughput, latency tails, memory, and energy. A mean runtime alone does not certify a real-time service.

Hardware and layout evidence

Multilayer layouts. Mathews and colleagues (2026) introduced a hardware-aware placement and routing method for qLDPC connectivity in a multilayer superconducting design. Explicit routes make geometric assumptions inspectable, but do not measure coupler fidelity, crosstalk, frequency allocation, control access, or fabrication yield. Primary report.

Repeated superconducting extraction. Wang and colleagues demonstrated two small qLDPC codes on a 32-transmon processor with long-range couplers, including periodic measurements of nonlocal weight-6 checks. The reported logical error rates were finite-device results under the chosen extraction and decoding procedure. The experiment establishes an implemented sparse nonlocal check circuit; it does not by itself establish suppression across an increasing asymptotically good family. Primary report.

A nonlocal trapped-ion block. Hong and colleagues (2024) prepared an entangled state of four logical qubits in a $[[25,4,3]]$ block on trapped-ion hardware and compared it with a physical GHZ-state reference. Their logical fidelity statement included postselection, with more than 98% of outcomes retained. Its meaningful boundary is a finite task with a declared reference and acceptance rule, not a general claim about scaling all nonlocal codes. Primary report.

Reconfigurable-atom and modular proposals offer other ways to realize sparse nonlocal interactions. Motion, link generation, synchronization, and buffering must be costed rather than treated as free connectivity. Their general requirements remain in the architecture bridge.

Logical operations and asymptotic protocols

Constant space and polylogarithmic time. Tamiya, Koashi, and Yamasaki proved a fault-tolerance result with these overhead scalings under the paper’s circuit, fault, parallelization, and classical-processing model. The theorem concerns a family of compiled circuits and its asymptotic resource ratios; it does not give a platform-independent finite overhead or an experimentally achieved runtime. Primary report.

Gauged logical measurements. Williamson and Yoder constructed logical measurement procedures with auxiliary-qubit cost linear in the measured operator’s weight up to polylogarithmic factors, under their construction conditions. Turning that result into a device operation requires an explicit auxiliary graph, extraction schedule, noise model, and decoding procedure. Primary report.

Transversal Clifford compilation. Malcolm and colleagues (2026) introduced QLDPC code families with efficient logical Clifford compilation and reported circuit-noise simulations of depth-126 logical circuits. That evidence concerns code construction and simulated logical operations; a universal hardware architecture also needs a non-Clifford mechanism and its full resource account. Primary report.

Evidence map retained from the cutoff

• Established theory: asymptotically good code families and protected logical-operation constructions, with their stated hypotheses.
• Conditional finite-code evidence: memory and gate advantages in specified circuit simulations and model comparisons.
• Bounded implementation evidence: repeated sparse nonlocal checks and multi-logical finite-block operations in the cited hardware experiments.
• Active integration question: sustained accuracy and decoder/control timing across increasing protection levels, with realistic connectivity and calibrated logical operations.
• Not established by this record: lower complete delivered cost for a useful algorithm on an integrated qLDPC hardware architecture.

This map classifies the selected evidence available to the snapshot. It does not assert that every result published before the cutoff was surveyed or that its open questions remain unchanged after that date.

Open problems retained from the cutoff

Find finite families, not isolated records

A useful family needs several blocks with increasing protection, compatible connectivity, known logical bases, and a common decoder. Optimizing one $[[n,k,d]]$ instance can produce a record that has no clean successor.

The search objective should include

$$\Phi = \alpha\frac{k}{n} +\beta\frac{d}{n} -\gamma w -\zeta C_{\mathrm{embed}} -\xi C_{\mathrm{decode}},$$

with coefficients tied to a hardware and workload model. Maximizing $k$ or $d$ alone is not enough.

Such a weighted score is only a search heuristic: its terms need specified normalizations, and changing the weights can change the winner. Enforce hard connectivity, accuracy, and timing constraints first, then retain the Pareto tradeoffs between feasible designs. A high score does not establish lower delivered cost or a threshold.

Measure range-dependent and correlated faults

Long couplers, global beams, shared modes, transport operations, and photonic links create fault structure unlike independent nearest-neighbor depolarizing noise. A qLDPC code’s nonlocal graph can either disperse a local hardware fault or align with a common-mode event.

Experiments need detector correlations conditioned on:

• edge length and routing layer;
• simultaneous-gate pattern;
• movement distance or motional mode;
• coupler crossings and shared controls;
• leakage and loss;
• calibration age;
• cosmic-ray or burst monitors.

A decoder trained on independent faults can turn model mismatch into a logical error floor.

Co-design decoder and control without circular validation

The syndrome stream can update both the logical frame and physical calibration. If the same learned model controls the device and scores its performance, it may suppress the diagnostics that reveal its own mistakes. Holdout detectors, periodic blind tests, injected faults, and independent logical observables are needed.

Make hardware yield part of code selection

A high-rate block may be sensitive to a few missing long edges. Code puncturing, graph repair, spare couplers, and rerouting can preserve function, but each changes distance and decoder behavior. The code-design loop should output a distribution over fabricated devices, not one perfect graph.

Benchmark logical operations at the same protection level

A memory round, a transversal gate, a gauged measurement, and a teleportation step expose different spacetime regions. Claims that gates perform “near memory” should use matched distance, elapsed time, decoder, acceptance, and logical observables. Multi-logical correlation is especially important when one operation acts across a high-rate block.

Establish a delivered-workload crossover

The strongest demonstration would compile the same nontrivial logical workload into a qLDPC architecture and a mature local-code architecture, allocate the same failure budget, and execute or emulate every physical and classical stage with measured parameters. The result should report physical qubits, qubit-time, energy, acceptance, wall-clock time, and verifier cost.

What Would Change the Assessment?

The historical assessment would need revision in light of evidence such as:

• hardware logical-error suppression across at least three increasing qLDPC blocks under comparable circuits and decoding;
• a qLDPC logical memory that beats a matched local-code reference in both physical footprint and elapsed-time-normalized performance;
• sustained decoding at target syndrome bandwidth with reported 99.9- or 99.99-percentile latency and fault recovery;
• a fabricated nonlocal layout whose measured edge-error and crosstalk distributions support the projected circuit threshold;
• a universal logical operation set on one scalable qLDPC family with measured distance preservation and accepted throughput;
• an end-to-end resource estimate grounded in measurements from all major subsystems, with sensitivity analysis and reproducible compilation;
• independent reproduction of a finite-block crossover on another device or platform.

A higher asymptotic exponent, a larger simulated block, or a new decoder record is valuable but does not alone establish a system crossover.

Graduate entry project: a finite-code crossover audit

Added on 11 October 2026, this project uses the retained August evidence without changing its cutoff. Reproduce a small bivariate-bicycle memory comparison against a surface-code reference at equal logical-qubit count and elapsed storage time. Start with the published independent circuit-noise model, then vary long-range gate error and decoder processing time separately.

Deliver detector samples, confidence intervals, physical-qubit and qubit-time budgets, and a crossover diagram. A workstation and public stabilizer/decoding software suffice for modest codes; rare-event targets require an explicit sampling budget. The baseline must reproduce the original model before adding realism. Failure tests include lost long edges, a decoder trained on the wrong noise model, and time normalization that includes slower nonlocal extraction.

Progress to research by using measured range-dependent errors or a realistic placement constraint to predict where a finite family wins or loses. A result showing no crossover in the accessible regime is informative. A single favorable code instance under freely chosen noise is not evidence of an integrated architectural advantage.

Separate code validity, decoder success, and memory performance

Before sampling, verify the binary CSS check condition $H_XH_Z^{\mathsf T}=0$ modulo two and calculate $k=n-\operatorname{rank}H_X-\operatorname{rank}H_Z$. Fix explicit logical Pauli representatives. A decoder correction with the observed syndrome is not necessarily successful: the residual error may commute with every check but act as a nontrivial logical operator. Classify residuals modulo the stabilizer group, testing each logical component and the event “any logical failure in the block.” The code foundations own the construction and equivalence relations; these checks make the research comparison reproducible.

If $p_j$ is the marginal failure probability of logical qubit $j$ in a specified experiment, the block failure probability obeys

$$\max_j p_j\leq p_{\rm block}\leq\min\!\left(1,\sum_jp_j\right).$$

The often-used conversion $1-(1-p)^k$ additionally assumes independent, equal-rate logical failures. It can be wrong for a shared high-rate block. For instance, if all $k$ logical qubits fail together with probability $p$, every marginal equals $p$ and the block probability is also $p$, not $1-(1-p)^k$. Preserve the joint logical-error samples to determine which failure events matter to the workload. Likewise, do not convert a final logical parity-flip probability into an independent per-round hazard without stating a stochastic model: repeated Pauli flips can cancel.

The $[[144,12,12]]$ memory’s 288 physical qubits give 24 physical qubits per encoded logical qubit only when all 12 are useful. A workload occupying six still requires the block and gives 48 per occupied logical qubit, before routing or logical-operation ancillas. This arithmetic does not overturn the cited comparison; it exposes an occupancy assumption that a new workload must revisit. Compare elapsed storage time and block-failure targets before comparing qubit-time, since a slower extraction round changes both noise exposure and the classical deadline.

A six-week audit with numerical stopping rules

In weeks 1–2 reproduce the checks, logical basis, and a published moderate-error memory point where failures are observable. In weeks 3–4 run both architectures at matched storage durations with the same acceptance convention and report binomial uncertainty over independent complete trials. In weeks 5–6 vary one hardware penalty and one decoder deadline, testing held-out parameter points near the predicted crossover. Preserve the extraction schedules and actual software configuration; recording only $[[n,k,d]]$ is insufficient.

At small failure probability $p$, $M$ independent Bernoulli trials have relative sampling error approximately $1/\sqrt{Mp}$. About 100 observed failures are needed for roughly 10% relative standard error. Directly studying $p=10^{-6}$ therefore requires order $10^8$ trials; zero failures in $10^6$ trials do not establish that target. Use a feasible moderate-error regime first. Continue to rare-event methods only with independently tested reweighting and uncertainty estimates. If the crossover moves more than its claimed width under finite-sample uncertainty, the deliverable is a bound on its location, not a sharp winning region.

Entry reading for a finite-code study

Start with Bravyi and colleagues for the complete finite-memory circuit and noise model. Read Hillmann and colleagues or Ye, Wecker, and Delfosse next to choose a reproducible decoder and measure its runtime distribution. Then use Mathews and colleagues to replace ideal connectivity by an explicit layout, and Wang and colleagues to see what small-device extraction actually establishes. The Tamiya, Williamson–Yoder, and Malcolm results address logical computation under different constructions and assumptions; they should guide a next-stage operation study rather than be spliced together as if they described one demonstrated architecture.

References

• S. Bravyi et al., “High-threshold and low-overhead fault-tolerant quantum memory,” Nature 627, 778–782 (2024). doi:10.1038/s41586-024-07107-7
• T. Hillmann et al., “Localized statistics decoding for quantum low-density parity-check codes,” Nature Communications 16, 8214 (2025). doi:10.1038/s41467-025-63214-7
• Y. Hong, E. Durso-Sabina, D. Hayes, and A. Lucas, “Entangling four logical qubits beyond break-even in a nonlocal code,” Physical Review Letters 133, 180601 (2024). doi:10.1103/PhysRevLett.133.180601
• Alexander J. Malcolm et al., “Computing efficiently in QLDPC codes,” Nature Communications 17, 7286 (2026). doi:10.1038/s41467-026-73061-9
• M. Mathews et al., “Placing and routing quantum LDPC codes in multilayer superconducting hardware,” npj Quantum Information 12, 114 (2026). doi:10.1038/s41534-026-01243-w
• Shiro Tamiya, Masato Koashi, and Hayata Yamasaki, “Fault-tolerant quantum computation with polylogarithmic time and constant space overheads,” Nature Physics 22, 27–32 (2026). doi:10.1038/s41567-025-03102-5
• K. Wang et al., “Demonstration of low-overhead quantum error correction codes,” Nature Physics 22, 308–314 (2026). doi:10.1038/s41567-025-03157-4
• D. J. Williamson and T. J. Yoder, “Low-overhead fault-tolerant quantum computation by gauging logical operators,” Nature Physics 22, 598–603 (2026). doi:10.1038/s41567-026-03220-8
• M. Ye, D. Wecker, and N. Delfosse, “Beam search decoder for quantum low-density parity-check codes,” PRX Quantum 7, 033002 (2026). doi:10.1103/6k5x-ztqt